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thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 1 / 17 thcv2 20 v - by - one? hs high - speed vide o data receiver general description thcv220 is designed to support video data transmission between the host and display. one high - speed lane can carry up to 32bit data and 3 bits of synchronizing signals a t a pixel clock frequency from 7.5 mhz to 93 mhz. it has one high - speed data lane and, maximum serial data rate is 3. 75 gbps/lane. width link ttl clock freq. 24bit si/so 10mhz to 125mhz 32bit si/so 7.5mhz to 93mhz si/so : single - in/single - out, features ? color depth selectable: 24(8*3)/32(10*3)bit ? single link ? ac coupling for high speed lines ? wide range supply voltage 2. 3 - 3 . 6 v ? package: 64 pin qfn ? wide frequency range ? cdr requires no external freq. reference ? spread spectrum clocking tolerant up to 30 khz/ ? 0. 5% (center spread) ? v - by - one ? hs standard ver.1. 4 compliant ? aec - q100 esd protection block diagram d e s e r i a l i z e r c d r f o r m a t t e r t h c v 2 2 0 r 9 - r 0 g 9 - g 0 b 9 - b 0 c o n t 2 , c o n t 1 h s y n c v s y n c d e c l k o u t c o l l f s e l r f p d n o e b e t l a t e n t t l d r v c m o s o u t p u t r x p r x n c o n t r o l s h t p d n l o c k n l d o a v c c b e t o u t c a p o u t c a p i n a v c c
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 2 / 17 contents page general description ................................ ................................ ................................ ................................ ................. 1 features ................................ ................................ ................................ ................................ ................................ ... 1 block diagram ................................ ................................ ................................ ................................ ........................ 1 pin configuration ................................ ................................ ................................ ................................ ..................... 3 pin description ................................ ................................ ................................ ................................ ........................ 4 functional description ................................ ................................ ................................ ................................ ............ 5 absolute maximum ratings* ................................ ................................ ................................ ................................ 10 recomm ended operating conditions ................................ ................................ ................................ .................... 10 electrical specifications ................................ ................................ ................................ ................................ ........ 10 ac timing diagrams and test circuits ................................ ................................ ................................ ................. 13 thcv220 output data mapping ................................ ................................ ................................ .......................... 15 package ................................ ................................ ................................ ................................ ................................ .. 16 notices and requests ................................ ................................ ................................ ................................ ............. 17
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 3 / 17 pin configuration test1 pdn r4 r5 vcc r6 r7 r8 r9 g4 g5 g6 g7 vcc g8 g9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lfsel 49 32 b4 htpdn 50 31 b5 lockn 51 30 clkout avcc 52 29 vcc test2 53 28 b6 capout 54 27 b7 capina 55 26 b8 gnd 56 25 b9 rxn 57 24 gnd rxp 58 (top view) 23 hsync gnd 59 65 expgnd 22 vsync laten 60 21 de betout 61 20 r2 bet 62 19 vcc col 63 18 r3 ttldrv 64 17 g2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe rf cont2 b1 vcc b0 g1 g0 r1 gnd r0 cont1 b3 vcc b2 g3 thcv220
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 4 / 17 pin description thcv220 pin description pin name pin # type description r9-r0 40,41,42,43,45, 46,18,20,9,11 o3 pixel data outputs g9-g0 33,34,36,37,38, 39,16,17,7,8 o3 pixel data outputs b9-b0 25,26,27,28,31, 32,13,15,4,6 o3 pixel data outputs cont1,2 12,3 o3 user defined data outputs. active only in 32bit mode. de 21 o3 de output vsync 22 o3 vsync output hsync 23 o3 hsync output clkout 30 o3 pixel clock output rxn/p 57,58 ci high-speed cml signal input. lockn 51 od3 lock detect output. must be connected to tx lockn with a 10k pull-up resistor. htpdn 50 od3 hot plug detect output. must be connected to tx htpdn with a 10k pull-up resistor. pdn 47 i3l power down input. h: normal operation l: power down ttldrv 64 i3 ttl outputs drive strength select input. h : normal drive strength l : weak drive strength oe 1 i3 output enable input. h: all cmos outputs enabled l: all cmos outputs disabled, except for lockn, htpdn col 63 i3 data width setting. h : 24bit l : 32bit lfsel 49 i3 frequency range setting. h: low frequency operation l: normal operation rf 2 i3 output clock triggering edge select input h: rising edge l: falling edge bet 62 i3 field-bet entry. h : field bet operation l : normal operation betout 61 o3 field bet result output. must be left open when not used. laten 60 i3 latch select input under field-bet operation h : latched result l : not latched result test1 48 - test pin, must be l for normal operation. test2 53 - test pin, must be l for normal operation. capout 54 - decoupling capacitor pins. this pin should be connected to external decoupling capacitors. recommended capacitance is 2.2uf capina 55 - reference input for analog circuit.must be tied capout. vcc 5,14,19,29, 35,44 ps digital power supply pins avcc 52 ps analog power supply pin gnd 10,24,56,59 ps ground pins expgnd 65 ps exposed pad ground *type symbol i3=3.3v cmos input, i3l=low speed 3.3v cmos input, o3=3.3v cmos output, od3=3.3v open drain output ci=cml input, ps=power supply
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 5 / 17 functional description functional overview with v - by - one ? hs proprietary encoding scheme and cdr (clock and dat a recovery) architecture, thcv 220 enable transmission of 8/10 bit rgb, 2bits of user - defined data (cont), synchronizing signals hsync, vsync, and de by a pair cable with minimal external components. thcv 220 automatically extracts the clock from the incoming data streams and converts the serial data into video data with de being high or synchronizing data with de being low, recognizing which type of serial data is being sent by the transmitter. and it outputs the recovered data in the form of cmos/ttl data. thcv 220 can operate for a wide range of a serial bit rate from 600mbps to 3. 75 gbps. it does not need any external frequency reference, such as a crystal oscillator. internal reference output/inpu t function (capout,capina ) an internal regulator produces the 1.2v (capout). this 1.2v linear regulator can not supply any other external loads. bypass capout to gnd with 2.2uf. capina supplies reference voltage for any internal analog circuit also. bypass capina to gnd with 0.1uf to remove high frequency noise. capout and capina must be tied together. analog power supply avcc is supposed to be stabilized with de - coupling capacitor and series noise filter (for example, ferrite bead). figure 1. connection of capout, capina and decoupling capacitor c a p o u t c a p i n a t h c v 2 2 0 2 . 2 u f 0 . 1 u f a v c c p o w e r s u p p l y
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 6 / 17 data enable figure 2 is the conceptual diagram of the basic operation of the chipset. thcv219 in figure 2 is an example of v - by - one ? hs transmitter. there are some requirements for de. figure 3 shows the timing diagram of it. figure 2. conceptual diagram of the basic operation of the chipset figure 3. data and synchronizing signals transmission timing diagram table 1. de requirement r / g / b c o n t v , h s y n c c t l 1 d e t h c v 2 2 0 t h c v 2 1 9 r / g / b c o n t v s y n c h s y n c d e = 1 , r / g / b , c o n t d e = 0 , c t l d e = 1 , v , h s y n c = f i x e d d e = 0 , v , h s y n c 0 c t l a r e p a r t i c u l a r a s s i g n e d b i t a m o n g r / g / b , c o n t t h a t c a n c a r r y a r b i t r a r y d a t a d u r i n g d e = 0 p e r i o d . h i g h l o w h i g h v a l i d d a t a v a l i d d a t a i n v a l i d i n v a l i d d e h s y n c v s y n c r g b c o n t t h c v 2 1 9 i n p u t * i n v a l i d v a l i d d a t a c l k i n l o w v a l i d d a t a i n v a l i d i n v a l i d v a l i d d a t a l o w h i g h i n v a l i d v a l i d d a t a ( r f = h ) h i g h l o w h i g h v a l i d d a t a v a l i d d a t a k e e p t h e l a s t d a t a o f d e = l p e r i o d d e h s y n c v s y n c r g b c o n t v a l i d d a t a c l k o u t l o w v a l i d d a t a v a l i d d a t a l o w h i g h v a l i d d a t a ( r f = h ) k e e p t h e l a s t d a t a o f d e = l p e r i o d k e e p t h e l a s t d a t a o f d e = l p e r i o d p a r t i c u l a r a s s i g n e d b i t c t l i s t r a n s m i t t e d e x p e c t t h e f i r s t a n d l a s t p i x e l o f b l a n k i n g p e r i o d . o h t e r s a r e l o w f i x e d . t d e h t d e l t d e h t d e l k e e p t h e l a s t d a t a k e e p t h e l a s t d a t a k e e p t h e l a s t d a t a * r e f e r t o t h e d a t a s h e e t o f t h c v 2 1 9 f o r i n p u t o p e r a t i o n t h c v 2 2 0 o u t p u t symbol parameter min. typ. max. unit tdeh de=high duration 2trcp sec tdel de=low duration 2trcp sec
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 7 / 17 color depth and frequency range select function thcv 220 support a variety of data width and frequency range. refer to table 2 for details. table 2. operation mode select col lfsel description freq. range l l 32bit 15 to 93m h 32bit low frequency mode 7.5 to 30m h l 24bit 20 to 125m h 24bit low frequency mode 10 to 40m hot - plug function htpdn indicates connecting condition between the transmitter and the receiver. ht pdn of the transmitter side is h igh when the receiver is not active or not connected. then transmitter can enter into the power down mode. htpdn is set to l ow by the receiver when receiver is active and connects to the transmitter, and then transmitter must start up and transmit cdr training pattern for link training. htpdn is open drain output at the receiver side. pull - up resistor is needed at the transmitt er side. htpdn connection between the transmitter and the receiver can be omitted as an application option. in this case, htpdn at the transmitter side should always be taken as low. lock detect function lockn indicates whether the cdr pll is in the lock state or not. lockn at the transmitter input is set to high by pull - up resistor when receiver is not active or at the cdr pll training state. lockn is set to low by the receiver when cdr lock is done. then the cdr training mode finishes and transmitter shi fts to the normal mode. lockn is open drain output at the receiver side. pull - up resistor is needed at the transmitter side. when htpdn is included in an application, the lockn signal should only be considered when the htpdn is pulled low by the receiver. figure 4. hot - plug and lock detect scheme v c c ( t x s i d e ) h t p d n l o c k n 1 0 k h t p d n l o c k n t h c v 2 2 0 1 0 k v c c ( t x s i d e ) h t p d n l o c k n h t p d n l o c k n t h c v 2 2 0 1 0 k w i t h h t p d n c o n n e c t w i t h o u t h t p d n c o n n e c t v - b y - o n e ? h s t x v - b y - o n e ? h s t x
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 8 / 17 drive select function ttl drv pin controls ttl output strength. see table 3 . table 3. drive select function table ttl drv description l weak ttl output strength h normal ttl output strength power down function setting the pdn pin low places thcv220 in the power - down mode. i nternal circuitry turns off and the cmos outputs drives low or hi - z depends on oe pin . table 4. power down function table pdn description l power down h normal operation output enable function oe pin select cmos/ttl output states. it is enabled with oe=h. when oe=l, cmos/ttl output s turns h i gh - z. see table 5 . table 5. oe function table pdn oe cmos/ttl output * l hi - z l h low fixed h normal operation
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 9 / 17 field bet operation in order to help users to check valid ity of cml high - speed serial line , thcv220 has an operation mode in which they act as a bit error tester (bet). thcv219 which is an example of tx device also has bet function mode. in this mode, thcv219 internally generates test pattern which is then serialized onto the cml high - speed line . thcv220 receives the data stream and checks bit errors. this "field bet" mode is activated by setting bet= h both on thcv219 and thcv220. the gen erated data pattern is then 8b/10b encoded, scrambled, and serialized onto the cml channel. as for thcv220, the internal test pattern check circuit gets enabled and reports result on betout pin. the betout pin goes low whenever bit errors occur, or it stay s high when there is no bit error. please refer to table 6 . user can select two kinds of check result, latched - result or not latched result. the latch is res et by setting laten = l . table 6. field bet operation pin settings thcv219 thcv220 condition bet bet laten operation output latch select l l l normal operation - h forbidden - h h l field bet operation not latched result h h h latched result table 7. thcv220 field bet result betout output l bit error occurred h no error figure 5. field bet configuration t h c v 2 1 9 t h c v 2 2 0 c l k i n b e t = h b e t = h t e s t p a t t e r n c h e c k e r t e s t p a t t e r n g e n e r a t o r t t l d a t a i n p u t s a r e i g n o r e d b e t o u t t e s t p o i n t f o r f i e l d b e t l a t e n
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 10 / 17 absolute maximum ratings* ? absolute maximum ratings are those values beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of electrical characteristics specify conditions for device operation. recommended operating conditions electrical specifications cmos dc specifications min. typ. max. unit -0.3 - +4.0 v -0.3 - vcc+0.3 v -0.3 - vcc+0.3 v -0.3 - +4.0 v -0.3 - capina+0.3 v -30 - 30 ma -55 - +125 - - +125 - - +260/10sec - - 3.9 w parameter supply voltage(vcc,avcc) cmos input voltage cmos output voltage output current storage temperature cmos open drain output voltage cml receiver input voltage junction temperature reflow peak temperature/time maximum power dissipation @+25 min. typ. max. unit 2.3 2.5 2.7 v 2.6 2.8 3.0 v 3.0 3.3 3.6 v -40 85 parameter operating temperature supply voltage vcc,avcc over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit iozh output leak current high in hi-z state oe=l -10 +10 ua iozl output leak current low in hi-z state oe=l -10 +10 ua iih input leak current high -10 +10 ua iil input leak current low -10 +10 ua vcapout regulator output voltage 1.20 v vcc=3.30.3v symbol parameter conditions min. typ. max. unit i3 2.0 vcc v i3l 2.1 vcc v i3 0 0.8 v i3l 0 0.7 v ttldrv=l,ioh=-4ma ttldrv=h,ioh=-8ma low level output voltage open drain output buffer iol=2ma 0.2 ttldrv=l, iol=4ma 0.4 ttldrv=h, iol=8ma 0.4 vol v low level output voltage cmos output buffer vil low level input voltage vcc v voh high level output voltage cmos output buffer 2.4 vih high level input voltage vcc=2.80.2v symbol parameter conditions min. typ. max. unit i3 1.8 vcc v i3l 1.9 vcc v i3 0 0.7 v i3l 0 0.6 v ttldrv=l,ioh=-2ma ttldrv=h,ioh=-4ma low level output voltage open drain output buffer iol=2ma 0.2 ttldrv=l, iol=2ma 0.4 ttldrv=h, iol=4ma 0.4 vcc v vol v low level output voltage cmos output buffer voh high level output voltage cmos output buffer 2.0 vih high level input voltage vil low level input voltage
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 11 / 17 cml dc specifications supply currents vcc=2.50.2v symbol parameter conditions min. typ. max. unit i3 1.7 vcc v i3l 1.6 vcc v i3 0 0.7 v i3l 0 0.5 v ttldrv=l,ioh=-2ma ttldrv=h,ioh=-4ma low level output voltage open drain output buffer iol=2ma 0.2 ttldrv=l, iol=2ma 0.4 ttldrv=h, iol=4ma 0.4 vcc v vol v low level output voltage cmos output buffer voh high level output voltage cmos output buffer 2.0 vih high level input voltage vil low level input voltage over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit vrth cml differential input high threshold 50 mv vrtl cml differential input low threshold -50 mv irih cml input leak current high pdn=l, rxp/n=1.2v 15 ua iril cml input leak current low pdn=l, rxp/n=gnd 15 ua irrih cml input current high rxp/n=1.2v 1.6 ma irril cml input current low rxp/n=gnd -4.6 ma rrin cml differential input resistance 80 100 120 over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit irccw receiver supply current (worst case pattern) cload=8pf col=l 170 ma irccs receiver power down supply current pdn=l all inputs =fixed lorh 1.2 10 ma
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 12 / 17 switching characteristics over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit trbit unit interval 267 1666 psec col=h, lfsel=l 8 50 ns col=h, lfsel=h 25 100 ns col=l, lfsel=l 10.67 66.66 ns col=l, lfsel=h 33.34 133.33 ns trch clkout high time trcp/2 ns trcl clkout low time trcp/2 ns tdout ttl data out period trcp ns col=h 13.0trcp+3.5 ns col=l 12.4trcp+3.5 ns trpd power on to pdn high delay 0 ns trhpd0 pdn high to htpdn low delay 10 ms trhpd1 pdn low to htpdn high delay 10 us trpll0 training pattern input to lockn low delay 10 ms trpll1 pdn low to lockn high delay 10 us trlck0 lockn low to ttl output delay 5 ms trlck1 lockn high to ttl low-fixed delay 0 ns clkout period input data to output clock delay trdc trcp vcc=3.30.3v symbol parameter conditions min. typ. max. unit ttldrv=l 0.45trcp-2.0 ns ttldrv=h 0.45trcp-1.5 ns ttldrv=l 0.45trcp-2.0 ns ttldrv=h 0.45trcp-1.5 ns clock ttldrv=l 1.0 2.0 ns data ttldrv=l 2.0 3.6 ns clock ttldrv=h 0.8 1.6 ns data ttldrv=h 1.6 2.4 ns clock ttldrv=l 1.0 2.0 ns data ttldrv=l 2.0 3.6 ns clock ttldrv=h 0.8 1.6 ns data ttldrv=h 1.6 2.4 ns trs ttl data setup to clkout trh ttl data hold to clkout ttlh ttl low to high transition time tthl ttl high to low transition time vcc=2.80.2v symbol parameter conditions min. typ. max. unit ttldrv=l 0.45trcp-2.5 ns ttldrv=h 0.45trcp-2.0 ns ttldrv=l 0.45trcp-2.5 ns ttldrv=h 0.45trcp-2.0 ns clock ttldrv=l 1.2 2.4 ns data ttldrv=l 2.4 4.2 ns clock ttldrv=h 0.8 2.2 ns data ttldrv=h 1.6 2.8 ns clock ttldrv=l 1.2 2.4 ns data ttldrv=l 2.4 4.2 ns clock ttldrv=h 0.8 2.2 ns data ttldrv=h 1.6 2.8 ns trs ttl data setup to clkout trh ttl data hold to clkout ttlh ttl low to high transition time tthl ttl high to low transition time vcc=2.50.2v symbol parameter conditions min. typ. max. unit ttldrv=l 0.45trcp-2.5 ns ttldrv=h 0.45trcp-2.0 ns ttldrv=l 0.45trcp-2.5 ns ttldrv=h 0.45trcp-2.0 ns clock ttldrv=l 1.2 2.4 ns data ttldrv=l 2.4 4.2 ns clock ttldrv=h 0.8 2.2 ns data ttldrv=h 1.6 2.8 ns clock ttldrv=l 1.2 2.4 ns data ttldrv=l 2.4 4.2 ns clock ttldrv=h 0.8 2.2 ns data ttldrv=h 1.6 2.8 ns ttl data setup to clkout trh ttl data hold to clkout ttlh ttl low to high transition time trs tthl ttl high to low transition time
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 13 / 17 ac timing diagrams and test circuits cmos/ttl output switching characteristics figure 6. cmos/ttl output switching timing diagrams and test circuit figure 7. cml buffer scheme 2 0 % 8 0 % c l = 8 p f r d = 1 0 t e s t p o i n t 2 0 % 8 0 % t t l h t t h l t x p r x p t x n r x n v t e r m 0 . 9 v ( t y p ) z d i f f = 1 0 0 o h m c = 7 5 2 0 0 n f 5 0 o h m g n d v - b y - o n e ? h s t x t h c v 2 2 0 c m l t r a n s m i t t e r c m l r e c e i v e r 5 0 o h m c = 7 5 2 0 0 n f v c c / 2 v c c / 2 v c c / 2 v c c / 2 v c c / 2 t r c p t r s t r h t d o u t t r c h ( r f = l ) t r c l ( r f = h ) r f = l r f = h r 9 - 0 , g 9 - 0 , b 9 - 0 c o n t 1 , c o n t 2 h s y n c , v s y n c d e c l k o u t t r c h ( r f = h ) t r c l ( r f = l )
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 14 / 17 latency characteristics figure 8. thcv220 latency lock and unlock sequence figure 9. thcv220 sequence v d i f f = ( r x p ) - ( r x n ) c l k o u t v c c / 2 t r c p p i x e l 1 s t b i t r / f = l r / f = h v c c / 2 v c c / 2 r 9 - 0 , g 9 - 0 , b 9 - 0 c o n t 1 , c o n t 2 h s y n c , v s y n c d e t r d c r x p / n f r o m v - b y - o n e ? h s t x h t p d n p d n l o c k n c l k o u t s o l i d l i n e : r f = h i g h d a s h e d l i n e : r f = l o w t r a i n i n g p a t t e r n n o r m a l p a t t e r n v c c r 9 - 0 , g 9 - 0 , b 9 - 0 c o n t 1 , c o n t 2 h s y n c , v s y n c d e l o w t r p d t r h p d 0 t r h p d 1 t r p l l 0 t r l c k 0 t r p l l 1 t r l c k 1 t r a i n i n g p a t t e r n t r a i n i n g p a t t e r n s o l i d l i n e : r f = h i g h d a s h e d l i n e : r f = l o w l o w l o w l o w l o w t r p l l 0 t r l c k 0 t r l c k 1 v a l i d d a t a p a t t e r n v a l i d d a t a p a t t e r n n o r m a l p a t t e r n
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 15 / 17 thcv220 out put data mapping table 8. cmos/ttl output data mapping for thcv220 *1 ctl bits, which are carried during de=low except the 1 st and the last pixel. 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r0 *1 - r0 - d30 r1 *1 - r1 - d31 r2 r0 r2 r2 d0 r3 r1 r3 r3 d1 r4 r2 r4 r4 d2 r5 r3 r5 r5 d3 r6 r4 r6 r6 d4 r7 r5 r7 r7 d5 r8 r6 r8 r8 d6 r9 r7 r9 r9 d7 g0 *1 - g0 - d28 g1 *1 - g1 - d29 g2 g0 g2 g2 d8 g3 g1 g3 g3 d9 g4 g2 g4 g4 d10 g5 g3 g5 g5 d11 g6 g4 g6 g6 d12 g7 g5 g7 g7 d13 g8 g6 g8 g8 d14 g9 g7 g9 g9 d15 b0 *1 - b0 - d26 b1 *1 - b1 - d27 b2 *1 b0 *1 b2 b2 d16 b3 *1 b1 *1 b3 b3 d17 b4 *1 b2 *1 b4 b4 d18 b5 *1 b3 *1 b5 b5 d19 b6 *1 b4 *1 b6 b6 d20 b7 *1 b5 *1 b7 b7 d21 b8 *1 b6 *1 b8 b8 d22 b9 *1 b7 *1 b9 b9 d23 cont1 *1 - cont1 - d25 cont2 *1 - cont2 - d24 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de symbol defined by v-by-one? hs data signals receiver output pin name
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 16 / 17 package l a s e r m a r k f o r p i n 1 9 . 0 0 . 6 5 0 . 9 m a x t o p v i e w 9 . 0 b o t t o m v i e w 6 . 0 0 6 . 0 0 1 . 1 0 0 . 4 5 1 . 1 0 0 . 5 0 . 2 5 0 . 4 1 1 6 1 7 3 2 3 3 4 8 4 9 6 4 p i n 1 i d 0 . 2 0 r 0 . 0 9 r s i d e v i e w
thine electronics, inc. security e thcv220_rev. 2. 3 0 _e copyright ? 201 7 thine electronics , inc. 17 / 17 notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or o missions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know - how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permissio n is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio - video device, office automation device, communication device, consumer electronics, smartphone, feature phone , and amusement machine device. thi s product must not be used for applications that require extremely high - reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine ele ctronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified p roduct only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevi table to a semi - conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is n ot designed to be radiation - proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product . except where mandated by applicable law or deemed necessary by thine based on the user s request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damage may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp http://www.thine.co.jp

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